1. Field of the Invention
This invention relates generally to integrated circuit testing, and more particularly to methods for determining logic speed in integrated circuits.
2. Description of the Related Art
Integrated circuits (ICs) are the cornerstones of myriad computational systems, such as personal computers and communications networks. As such, purchasers of such systems have come to expect significant improvements in speed performance over time, which encourages system designers to select ICs that guarantee superior speed performance. In an effort to increase chip speed, quality, and density of internal circuit components, chip manufacturers often attempt to maximize fault coverage when testing their IC designs. A common industry design practice is to make the IC design scannable by implementing scan cells. Among many types of scan cells, the most common scan cell is the “muxed-scan,” or also referred to herein as a “scan flop.”
FIG. 1A illustrates a conventional scan flop 100 having a multiplexer 102 and a D flip flop 104. Generally, the scan flop 100 has a system data input (DI) and a scan data input (SI) that are respectively connected to the multiplexer 102. The muliplexer 102 is configured to receive a scan enable (SE) and output a signal to a D input of the D flip-flop 104. The scan flop 100 also receives a clock signal (CP), which is communicated to the D flip-flop 104. In addition, output pins Q and NQ are also selectively output from the D flip-flop 104. The scan flop is therefore configured to operate in one of two modes. The first mode is a “system” mode (also known as the functional mode), and the second mode is a “scan” mode (also known as the test mode).
FIG. 1B illustrates a simplified semiconductor chip 101 having a scan chain that is made up of a plurality of interconnected scan flops 100. In actuality, when a full-scan design is implemented for a semiconductor chip 101, many more scan chains are integrated into the IC design to enable the scan test to achieve the highest fault coverage. However, for this simplified example, the scan data input (SI) of the first scan flop 100 of the scan chain is connected to a pad 110, and the output pin Q of the last scan flop 100 is connected to a pad 112. Also shown is a clock (CLK) pad connected to each of the clock signals (CP) of the individual scan flops 100. The output pins Q of each scan flop 100 of the scan chain are connected to the scan data input (SI) of a subsequent scan flop 100. In this common scan chain design, non-scan chain logic 106 is also connected to the output pins Q and the scan data inputs (SI). Additionally, non-scan chain logic 106 may be connected to the output pins NQ.
When the scan flop 100 is in the system mode, the scan enable (SE) signal is constrained to ground, such that the scan flop 100 operates identically to the D-flip-flop 104. In the scan mode, the scan enable (SE) signal is active high in shifting. In general, a test vector is scanned into each one of the scan flops 100 one clock at a time. Therefore, if a particular scan chain has one thousand scan flops 100, the scan chain would take one thousand clock shifting cycles to load.
Although, the above described scan cell testing model can provide good fault coverage when testing IC designs, chip manufacturers often need to test all process corners to avoid later system errors. As is well known, ICs are comprised of logic gates. However, the speed of the logic gates can vary from one IC to another because of silicon manufacturing process variances. As a result, ICs need to be tested to determine the speed, relative to the process, of each chip. Moreover, variances in operating voltage can affect the speed of an IC. Hence, ICs need to be tested to determine the affect various voltage levels have on the operating speed of each IC.
In addition to scan cells as described above, ring oscillation has been used to test IC speed. FIG. 2 is a schematic diagram showing a conventional ring oscillator 200. The ring oscillator 200 includes an inverter 202 coupled to a plurality of buffers 204, wherein the output of the last buffer 204 provides feedback to the input of the inverter 202. Generally, an odd number of inverters 202 and buffers 204 are used in order to oscillate the output signal at output pin 206 during operation. Hence, the inverter 202 inverts a signal applied to its input and provides the inverted signal to the buffers 204. The last buffer 204 feeds the inverted signal back to the inverter 202, which inverts the signal again, thus providing signal oscillation.
To test the IC speed, the output pin 206 is monitored to determine the frequency of the oscillation. The frequency can then be used to determine the speed of the IC. Unfortunately, the ring oscillator approach is complicated and highly layout dependent. For example, an extra output pin 206 is required, or a mux needs to be applied to an existing pin. In addition, the number of buffers and the size of the buffers must be determined based on the exact IC layout and existing RC delays, and space must be reserved for each ring oscillator used. These determinations require a great deal of planning and experimentation to generate the desired results.
In addition to ring oscillation, functional test vectors have been used to determine IC logic speed. In this technique, a functional test vector is run at speed to determine how fast the IC will operate. Unfortunately, several problems are associated with the approach. First, the composition of the test vector must be well planed in order for proper testing, thus again requiring a great deal of planning and experimentation to generate the desired results. Second, the testor used to test the IC must be able to drive the inputs and measure the outputs of the IC fast, often faster than many testor can operate. Third, the determination of the whether the test passed or failed is often difficult to establish, and further passing or failing only provides one threshold for sorting IC devices. For example, if parts A, B, and C all pass, there is no way to determine the relationships between the parts and there is no way to relate their passing to simulations. Moreover, there is no way to determine how fast the parts are or how slow they are.
In view of the foregoing, there is a need for methods for determining IC speeds relative to a process. The methods should allow determination of the affect of voltage changes on the ICs and should further allow correlation of ICs, within a particular process, into various speed grades. Further, the methods should be non-layout specific and relatively easy to implement and utilize.